The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a plurality of memory circuits and a memory test circuit mounted on the same chip, and to a recording medium on which data for preparing such a semiconductor device is recorded.
Semiconductor devices (LSIs) developed in recent years, such as ASICs, tend to have both logic circuits and a plurality of memory circuits mounted on a single chip.
Such a semiconductor device can achieve a higher data transfer rate (data transfer amount per unit time) between the logic circuits and the memory circuits, compared with that of a conventional semiconductor device. Further, such a semiconductor device requires no input/output circuits between the logic circuits and the memory circuits, and thus can achieve a reduction in the total power consumption, compared with a semiconductor device mounted with logic circuits and connected to a semiconductor device mounted with memory circuits.
A semiconductor device is subjected to an operation test prior to shipment to determine if the logic circuits and the memory circuits operate normally. That is, a semiconductor device is connected to a testing apparatus, and is operated in accordance with test signals supplied from the testing apparatus. The testing apparatus determines whether the semiconductor device is normal or not using the output signals of the semiconductor device.
As is well known, the memory circuits are subject, due to their structure, to memory cell defects and malfunctions caused, for example, by interference between memory cells. Therefore, it is required that the operation of the memory circuits alone be tested before that of the logic circuits. However, since the input/output terminals of the memory circuits are connected to the logic circuits, it is difficult to perform input/output operations with the memory circuits from outside the semiconductor device, because to do so requires pads for performing input/output operations with the memory circuits, and hence leads to an increase in the chip area of the semiconductor device.
To solve this problem, it has been considered to mount memory test circuits on a semiconductor device. However, as semiconductor devices become more and more multi-functional, the number of memory circuits mounted on a semiconductor device has increased, and if memory test circuits are mounted so as to correspond to the memory circuits on a one-to-one basis, the area occupied by the test circuits increases dramatically, thereby increasing the chip area and the cost of the semiconductor device. Thus, a test technique in which a plurality of memory circuits are tested using a smaller number of test circuits than the number of memory circuits is advantageous.
FIG. 1 is a schematic block diagram of a first conventional semiconductor device 1. The semiconductor device 1 includes a memory circuit 2 and a test circuit 3, which are formed on one chip together with logic circuits (not shown).
The memory circuit 2 has an input/output interface whose construction is analogous to that of an SDRAM (Synchronous Dynamic Random Access Memory). The test circuit 3 generates a control signal CMD, an address signal ADD, an operating clock signal CLK, and a data signal DATA, and outputs these signals to the memory circuit 2.
The memory circuit 2 receives the control signal CMD in synchronism with the clock signal CLK, and operates in a mode based on this control signal CMD. In the write mode, the memory circuit 2 receives an address signal ADD and a data signal DATA in synchronism with the clock signal CLK, and stores the data signal DATA in a cell whose address corresponds to the address signal ADD as cell information. In the read mode, the memory circuit 2 receives an address signal ADD in synchronism with the clock signal CLK, reads cell information stored in the cell whose address corresponds to the address signal ADD, and outputs the read information as a data signal DATA.
The test circuit 3 generates an expected value, compares the expected value with the value of the data signal DATA provided from the memory circuit 2, and outputs a determination signal DTRM generated based on the comparison result to a testing apparatus (not shown).
FIG. 2 is a schematic block diagram of a second conventional semiconductor device 4. The semiconductor device 4 includes a plurality (two in this example) of memory circuits 5a and 5b, and two test circuits 6a and 6b corresponding to the memory circuits 5a, 5b, respectively. The circuits 5a, 5b, 6a and 6b are formed on one chip together with logic circuits (not shown).
The test circuits 6a and 6b operate like the aforesaid test circuit 3. That is, the test circuit 6a applies to the memory circuit 5a a control signal CMD-1, an address signal ADD-1, a clock signal CLK-1, and a data signal DATA-1. The test circuit 6a compares the value of the data signal DATA-1 received from the memory circuit 5a with an expected value, and outputs a determination signal DTRM-1 based on the comparison result to a testing apparatus (not shown).
Further, the test circuit 6b applies to the memory circuit 5b a control signal CMD-2, an address signal ADD-2, a clock signal CLK-2, and a data signal DATA-2. The test circuit 6b compares the value of the data signal DATA-2 received from the memory circuit 5b with an expected value, and outputs a determination signal DTRM-2 based on the comparison result to the testing apparatus (not shown).
When the test circuits are mounted on the semiconductor device so as to correspond to the memory circuits on a one-to-one basis as described above, the chip area of the semiconductor device is dramatically increased. To overcome this problem, a method by which the operation of a plurality of memory circuits are tested using a single test circuit would be desirable. A third conventional semiconductor 7 device based on such a method is shown in FIG. 3.
The semiconductor device 7 includes a plurality (two in this example) of memory circuits 8a and 8b, and a test circuit 9. The circuits 8a, 8b and 9 are formed on one chip together with logic circuits (not shown).
The test circuit 9 tests the operation of the memory circuits 8a and 8b simultaneously. The reason is that when the memory circuits 8a and 8b are tested separately, it takes a lot of time, which leads to an increase in the cost of the semiconductor device 7.
The test circuit 9 applies to the memory circuit 8a a control signal CMD, an address signal ADD, and a clock signal CLK, each of which is generated to be used by the memory circuits 8a and 8b in common. Further, the test circuit 9 applies data signals DATA-1 and DATA-2, which are generated to be used individually, to the memory circuits 8a and 8b, respectively. This is because each of the memory circuits 8a and 8b uses a single terminal for both inputting and outputting data signals. If memory circuits, each having separate input and output terminals for transferring data signals, are used, a single data signal may be generated so that the memory circuits 8a and 8b can share such signal.
The test circuit 9 outputs to the testing apparatus (not shown) a determination signal DTRM having the result of a comparison made between the value of the data signal DATA-1 received from the memory circuit 8a and an expected value and the result of a comparison made between the value of the data signal DATA-2 received from the memory circuit 8b and the expected value. Thus, by using a single test circuit 9 to simultaneously test the two memory circuits 8a and 8b, the semiconductor device 7 prevents its chip area and testing time from increasing.
However, the third conventional the semiconductor device 7 encounters a problem concerning the distance between the test circuit 9 and each of the memory circuits 8a and 8b. That is, the wire length of a signal line between the test circuit 9 and the memory circuit 8b is longer than that between the test circuit 9 and the memory circuit 8a. There is a delay corresponding to the wire length to a signal output from the test circuit 9, and thus a lag between the times at which the memory circuits 8a and 8b receive such a signal.
FIG. 4(a) is a waveform chart of the input/output terminals of the test circuit 9; FIG. 4(b) is a waveform chart of the input/output terminals of the memory circuit 8a; and FIG. 4(c) is a waveform chart of the input/output terminals of the memory circuit 8b. 
Now, the test circuit 9 outputs a control signal CMD for a command xe2x80x9cACTxe2x80x9d in synchronism with the clock signal CLK at time t1. The memory circuit 8a receives the command at time t2, which is xcex94t1 past time t1, and the memory circuit 8b receives the same command at t3, which is xcex94t2 past time t1.
The memory circuits 8a and 8b operate in response to the command. The signals output by the memory circuits 8a and 8b reach the test circuit 9 while subjected to delays equal to the wire lengths similar to the signal which they receive. Therefore, the test circuit 9 receives data signals DATA-1 and DATA-2 from the memory circuits 8a and 8b at different time, respectively.
That is, the test circuit 9 receives the data signal DATA-1 from by the memory circuit 8a at time t4, and receives the data signal DATA-2 from the memory circuit 8b at time t5, which is later than time t4. Thus, the test circuit 9 cannot determine the operation of the memory circuit 8a and the operation of the memory circuit 8b at the same time. This requires that the test circuit 9 perform complicated determination operations, and which hinders the implementation of operation tests with a single test circuit.
An object of the present invention is to provide a semiconductor device which prevents the area occupied by a test circuit from increasing and performs simultaneous testing of a plurality of memory circuits.
In a first aspect of the present invention, a semiconductor device including a plurality of memory circuits and a test circuit for testing the plurality of memory circuits is provided. Test circuit includes a test section for controlling the plurality of memory circuits to perform a read operation and generating expected value data corresponding to read data from the plurality of memory circuits. A plurality of comparison/determination circuits are connected to the test section and the plurality of memory circuits, compare the read data and the expected value data, and generate determination signals.
In a second aspect of the present invention, a semiconductor device including a plurality of memory circuits, a test circuit for testing the plurality of memory circuits, and a plurality of signal correction circuits. The test circuit provides a control signal to the plurality of memory circuits to initiate a read operation, receives read data signals from the plurality of memory circuits and compares the read data signals with expected value data signals corresponding to the read data signals The plurality of signal correction circuits delays at least one of the control signal and the read data signals such that the read data signals reach the test circuit substantially simultaneously.
In a third aspect of the present invention, a recording medium on which hardware description language (HDL) data describing the behavior of a test circuit for testing a plurality of memory circuits is recorded is provided. The test circuit includes a test section and a comparison/determination circuit. The HDL data includes first and second data segments. The first data segment describes the behavior of the test section for controlling the plurality of memory circuits to perform a read operation, and generating expected value data corresponding to read data from the plurality of memory circuits. The second data segment describes the behavior of the comparison/determination circuits for comparing the read data and the expected value data and generating determination signals.
In a fourth aspect of the present invention, a recording medium on which hardware description language (HDL) data describing the behavior of a test circuit for testing a plurality of memory circuits is recorded is provided. The HDL data includes first and second data segments. The first data segment describes the behavior of the test circuit for providing a control signal to the plurality of memory circuits to perform a read operation, receiving read data signals from the plurality of memory circuits and comparing the read data signals with expected value data signals corresponding to the read data signals. The second data segment describes the behavior of a plurality of signal correction circuits for delaying at least one of the control signal and the read data signals such that the read data signals reach the test circuit substantially simultaneously.
In a fifth aspect of the present invention, a recording medium on which cell data about a test circuit for testing a plurality of memory circuits is recorded is provided. The cell data includes first and second cell data segments. The first cell data segment of a test section controls the plurality of memory circuits to perform a read operation and generates expected value data corresponding to read data from the plurality of memory circuits. The second cell data segment of a comparison/determination circuits for compares the read data and the expected value data and generates determination signals.
In sixth aspect of the present invention, a recording medium on which cell data about a test circuit for testing a plurality of memory circuits is recorded is provided. The data includes first and second cell data segments. The first cell data segment of the test circuit provides a control signal to the plurality of memory circuits to perform a read operation, receives read data signals from the plurality of memory circuits and compares the read data signals with expected value data signals corresponding to the read data signals. The second cell data segment of a plurality of signal correction circuits for delays at least one of the control signal and the read data signals such that the read data signals reach the test circuit substantially simultaneously.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.